LEADER 00000cam  2200000 a 4500 
001    213495304    
003    OCoLC 
005    20080722091723.0 
008    080313s2008    njua          001 0 eng   
010    2008011981 
020    0131860062 (pbk. : alk. paper) 
020    9780131860063 
035    213495304 
040    DLC|cDLC|dBAKER|dYDXCP|dBTCTA|dUKM|dC#P|dBWX|dCDX 
049    TXUM 
050 00 TK7870.23|b.L39 2008 
100 1  Lawday, Geoff,|d1946- 
245 12 A signal integrity engineer's companion :|breal-time test 
       and measurement and design simulation /|cGeoff Lawday, 
       David Ireland, and Greg Edlund. 
260    Upper Saddle River, NJ :|bPrentice Hall,|cc2008. 
300    xxxi, 460 p. :|bill. ;|c25 cm. 
440  0 Prentice Hall modern semiconductor design series. 
500    Includes index. 
505 0  Chip-to-chip timing and simulation -- Signal path analysis
       as an aid to signal integrity -- DDR2 case study -- Real-
       time measurements : probing -- Testing and debugging : 
       oscilloscopes and logic analysers -- Replicating real-
       world signals with signal sources -- Signal analysis and 
       compliance -- PCI express case study -- The wireless 
       signal. 
650  0 Electronic apparatus and appliances|xTesting. 
650  0 Electronic apparatus and appliances|xDesign and 
       construction. 
650  0 Signal processing|xSimulation methods. 
650  0 Switching circuits|xReliability. 
650  0 Oscillators, Electric|xTesting. 
700 1  Ireland, David,|d1957- 
700 1  Edlund, Greg. 
LOCATION CALL # STATUS
 Main Stacks  TK7870.23 .L39 2008    AVAILABLE