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Title Architecture of computing systems -- ARCS 2016 : 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings / Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich (eds.).
Imprint Switzerland : Springer, 2016.

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Description 1 online resource (xx, 402 pages) : illustrations
Series Lecture notes in computer science, 0302-9743 ; 9637
LNCS sublibrary. SL 1, Theoretical computer science and general issues
Lecture notes in computer science ; 9637. 0302-9743
LNCS sublibrary. SL 1, Theoretical computer science and general issues.
Note International conference proceedings.
Includes author index.
Available only to authorized UTEP users.
English.
Online resource; title from PDF title page (SpringerLink, viewed April 6, 2016).
Subject Computer architecture -- Congresses.
Genre Electronic books.
Conference papers and proceedings.
Electronic books.
Contents Intro; Preface; Organization; Invited Talks; Avinash Sodani, Chief Architect 'KnightsLanding' Xeon-Phi Processorat Intel Corporation; Michael Wong, IBM Corporation, XL C++Compiler Kernel Development; John Glossner, President of HSAF and CEOof Optimum Semiconductor Technologies; Contents; Configurable and In-Memory Accelerators; Towards Multicore Performance with Configurable Computing Units; Abstract; 1 Introduction; 2 Overview; 2.1 Design Flow and CCU Microarchitecture; 2.2 Backend Execution Example; 3 Compilers; 3.1 OmpSs Programming Model; 3.2 Logical Compiler; 3.3 Physical Compiler
4 Hardware Design4.1 rS and Interconnect; 4.2 Functional Units; 4.3 Read Register Buffer (RRB); 4.4 Write Register Buffer (WRB); 4.5 Configuration and Setup; 5 Experimental Testing; 5.1 Methodology; 5.1.1 Benchmarks; 5.1.2 Compilation; 5.1.3 Benchmark Analysis for Prototyping; 5.1.4 Software Simulators; 5.1.5 Hardware Prototypes; 5.2 Results; 5.2.1 Area; 5.2.2 Configuration Memory; 5.2.3 Performance; 5.2.4 Engine Utilization; 5.2.5 Frequency of Operation; 5.2.6 Power; 6 Conclusion; Acknowledgement; References
Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube1 Introduction; 2 Related Works; 3 The SMC Simulation Environment; 3.1 Design of PIM and Its Software Stack; 4 Experimental Results; 5 Conclusions; References; Network-on-Chip and Secure Computing Architectures; CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection Router; 1 Introduction and Related Work; 2 Motivation; 3 CASCADE Router Architecture; 4 Congestion Monitoring and Cycle Switching; 5 Experimental Setup; 6 Results and Analysis; 7 Conclusion; References
An Alternating Transmission Scheme for Deflection Routing Based Network-on-Chips1 Introduction; 2 Bufferless Deflection Routing; 3 TwoPhases; 3.1 Prerequisites and General Operating Mode; 3.2 Performance; 3.3 Optimality of Decomposition into Flits; 3.4 Pipelined Router Architectures; 4 Transmission Methods; 4.1 MultiFlit; 4.2 Serialization; 5 Evaluation; 6 Related Work; 7 Summary; References; Exzess: Hardware-Based RAM Encryption Against Physical Memory Disclosure; 1 Introduction; 2 Background; 2.1 PCI Express; 2.2 DMA Transfers and Device Memory; 3 Design and Implementation; 3.1 Threat Model
3.2 Design Rationale3.3 Exzess Architecture; 3.4 Exzess Implementation; 4 Evaluation; 4.1 Correctness; 4.2 Performance; 5 Related Work; 6 Discussion; 6.1 Limitations; 6.2 Future Work; 7 Conclusion; References; Hardware-Assisted Context Management for Accelerator Virtualization: A Case Study with RSA; 1 Introduction; 2 Related Work; 3 Baseline RSA Accelerator Architecture; 3.1 Montgomery's Modular Multiplication and Exponentiation; 3.2 Sharing an RSA Accelerator; 4 Tightly Integrated Virtual Accelerator Approaches; 4.1 Baseline Virtual RSA Accelerator Design Overview
4.2 Optimized Accelerator Virtualization Strategy -- Making Virtual Accelerator Out of Area Efficiency
Summary This book constitutes the proceedings of the 29th International Conference on Architecture of Computing Systems, ARCS 2016, held in Nuremberg, Germany, in April 2016. The 29 full papers presented in this volume were carefully reviewed and selected from 87 submissions. They were organized in topical sections named: configurable and in-memory accelerators; network-on-chip and secure computing architectures; cache architectures and protocols; mapping of applications on heterogeneous architectures and real-time tasks on multiprocessors; all about time: timing, tracing, and performance modeling; approximate and energy-efficient computing; allocation: from memories to FPGA hardware modules; organic computing systems; and reliability aspects in NoCs, caches, and GPUs.
Other Author Hannig, Frank, editor.
Cardoso, João M. P., editor.
Pionteck, Thilo, editor.
Fey, Dietmar, editor.
Schröder-Preikschat, W. (Wolfgang), editor.
Teich, Jürgen, 1964- editor.
Other Title 3-319-30694-4
Other Title ARCS 2016